1. Field of the Invention
The invention relates generally to Serial Attached SCSI (SAS) and more specifically relates to improved routing within SAS expanders.
2. Discussion of Related Art
In Serial Attached SCSI (SAS) systems, initiators (e.g., storage controllers implemented as Host Bus Adapters (HBAs)) manage the operations of one or more targets (e.g., storage devices or other functional circuitry components). SAS expanders couple the various SAS devices, forming a switched fabric through which point-to-point connections can be routed from initiators to targets. SAS expanders generally include physical links that are configured as logical ports, and generally also include switching circuitry and logic. A typical SAS expander can be configured to temporarily couple any of its ports to any other of its ports in order to establish a connection between devices. For example SAS standards allow for ports that consist of a single physical link (“narrow ports”), and also allow for “wide ports” made from multiple physical links that are logically configured together as a single entity. A wide port can enable greater bandwidth in communications between devices than a narrow port.
When communications are routed through a switched SAS fabric from an initiator to a target, each SAS expander receiving the communication consults routing information in memory in order to determine how to establish a connection to send the communication to its final destination. Because high levels of performance in SAS systems are generally desirable, routing information in a SAS expander may be accessed via a Content-Addressable Memory (CAM) (i.e., special hardware). The CAM can link SAS addresses with entries in memory, each entry in memory showing available ports of the expander that can be used to initiate a connection with a corresponding SAS address. For example, entries in the CAM may be pointers to entries in Random Access Memory (RAM) that list such available ports.
The RAM entries indicate which ports of the expander may be used to route an incoming communication to a requested SAS address. For example, there may be a unique RAM entry for each possible SAS address. Each entry may include a series of bits, and each bit may represent whether a corresponding PHY of the expander (i.e., a physical link along with associated transceiver elements and logic) can be used to route to that SAS address. When a wide port can be used to route requests through the SAS expander, the bit for each PHY of the wide port may be individually marked as available.
While CAMs provide a substantial performance benefit for routing functions in SAS expanders, CAMs remain expensive to implement, even for small amounts of memory (e.g., even several kilobytes). Furthermore, CAM and RAM structures used for routing take up valuable die space on SAS expanders that are produced as integrated circuits, which undesirably increases the size and cost of those SAS expanders. Still further, as the number of ports in a SAS expander increases, the size of these routing memory resources increases, and this adds to the cost and complexity of the expander.
Thus it is an ongoing challenge to balance competing objectives of value and performance when implementing routing memory structures in a SAS expander.